Text 65684, 91 rader
Skriven 2011-05-29 07:00:00 av TOM WALKER (1:123/140)
     Kommentar till en text av JEAN PARROT
Ärende: Still no 4GB
====================
JP> Tom, I just had a peek inside the machine, no jumper or none so identified
JP>pertaining to RAM. I even removed both sticks, either of them showed 2096128
JP>when in singly and in either DIMM socket too.

JP> The total remains at 3 Gs.  Strange, very strange !

Here is something to muddy the water a litle bit more. I am a pessimist
but it looks like all is lost(the Memory Above 3 gig that is!
****
Most x86 processors from the Pentium Pro onward do support physical
addresses up to 64 GB, the rest of the motherboard must participate in
allowing RAM above the 4GB point to be addressed by the CPU. Chipsets
and motherboards allowing more than 4 GB of RAM with x86 processors do
exist, but in the past, most of those intended for other than the
high-end server market supported only 4 GB of RAM.

This, however, is not sufficient to explain the "3 GB barrier" that
appears even when running some x86 versions of Microsoft Windows on
platforms that do support more than 4 GB of RAM.
[edit] Memory mapped I/O and disabled RAM

Modern personal computers are built around a set of standards that
depend on, among other things, the characteristics of the original PCI
bus. The original PCI bus supported 32-bit physical addresses and 32-bit
wide data transfers. PCI (and PCI Express, and AGP) devices present at
least some, if not all, of their host control interfaces via a set of
memory-mapped I/O locations (MMIO). The address space in which these
MMIO locations appear is the same address space as that used by RAM, and
while RAM can exist and be addressable above the 4 GB point, these MMIO
locations decoded by I/O devices cannot be. They are limited by PCI bus
specifications to addresses of 0xFFFFFFFF (232-1) and below. With 4 GB
or more of RAM installed, and with RAM occupying a contiguous range of
addresses starting at 0, some of the MMIO locations will overlap with
RAM addresses.

The BIOS and chipset are responsible for detecting these address
conflicts and disabling access to the RAM at those locations. Due to
the way bus address ranges are determined on the PCI bus, this disabling
is often at a relatively large granularity, resulting in relatively
large amounts of RAM being disabled.
[edit] Address remapping (the "memory hole")

x86 chipsets that support more than 4 GB of RAM typically also support
memory remapping (referred to in some BIOS setup screens as "memory hole
remapping"). In this scheme the BIOS detects the memory address conflict
and in effect relocates the interfering RAM so that it may be addressed
by the processor at a new physical address that does not conflict with
MMIO. On the Intel side, this support once was limited to server
chipsets; however, newer desktop chipsets like the Intel 955X and 965
and later support it as well. On the AMD side, the AMD K8 and later
processors' built-in memory controller supported it from the beginning.

As the new physical addresses are above the 4 GB point, addressing this
RAM does require that the operating system be able to use physical
addresses larger than 232.[11] This capability is provided by PAE. Note
that there is not necessarily a requirement for the operating system to
support more than 4 GB total of RAM, as the total RAM might be only 4
GB; it is just that a portion of it appears to the CPU at addresses in
the range from 4 GB and up.

This form of the 3 GB barrier affects one generation of MacBooks,
lasting 1 year (Core2Duo (Merom) - Nov 2006 to Oct 2007): the prior
generation was limited to 2 GB, while later generations (Nov 2007-Oct
2009) allowed 4 GB by supporting PAE and memory hole remapping, and
subsequent generations (late 2009 onwards) use 64-bit processors and
support over 4 GB.

Windows version dependencies

The final piece of the 3 GB barrier puzzle is a limit deliberately coded
by Microsoft into the "non-server," or "client," x86 editions of
Microsoft Windows: Windows XP, Windows Vista, and Windows 7. The 32-bit
(x86) versions of these are able to operate x86 processors in PAE mode,
and do so by default as long as the CPU present supports the NX bit.[13]
Nevertheless, these operating systems do not permit addressing of
physical memory above the 4 GB address boundary. This is not an
architectural limit; it is a limit imposed by Microsoft as a workaround
for driver compatibility issues that were discovered during testing.[14]

Thus, the "3 GB barrier" under x86 Windows "client" operating systems
can therefore arise in two slightly different scenarios. In both, RAM
near the 4 GB point conflicts with memory-mapped I/O space. Either the
BIOS simply disables the conflicting RAM; or, the BIOS remaps the
conflicting RAM to physical addresses above the 4 GB point, but x86
Windows client editions refuse to use physical addresses higher than
that, even though they are running with PAE enabled. The conflicting RAM
is therefore unavailable to the operating system whether it is remapped
or not.
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